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In integrated circuit design, physical design is a step in the standard design cycle which follows after the circuit design. At this step, circuit representations of the components (devices and interconnects) of the design are converted into geometric representations of shapes which, when manufactured in the corresponding layers of materials, will ensure the required functioning of the components. This geometric representation is called integrated circuit layout. This step is usually split into several sub-steps, which include both design and verification and validation of the layout.〔N. Sherwani, "Algorithms for VLSI Physical Design Automation", Kluwer (1998), ISBN 9780792383932〕 Modern day Integrated Circuit (IC) design is split up into ''Front-end design using HDLs'', ''Verification'', and ''Back-end Design'' or ''Physical Design''. The next step after Physical Design is the Manufacturing process or Fabrication Process that is done in the Wafer Fabrication Houses. Fab-houses fabricate designs onto silicon dies which are then packaged into ICs. Each of the phases mentioned above have ''Design Flows'' associated with them. These Design Flows lay down the process and guide-lines/framework for that phase. Physical Design flow uses the technology libraries that are provided by the fabrication houses. These technology files provide information regarding the type of Silicon wafer used, the standard-cells used, the layout rules (like DRC in VLSI), etc. ==Divisions== Typically, the IC physical design is categorised into Full custom & Semi-Custom Design. * Full-Custom: Designer has full flexibility on the layout design, no predefined cells are used. * Semi-Custom: Pre-designed library cells (preferably tested with DFM) are used, designer has flexibility in placement of the cells & routing.〔(Semi-Custom Design Flow )〕 One can refer ASIC for Full Custom design and FPGA for Semi-Custom design flows.The reason being that one has the flexibility to design/modify design blocks from Vendor provided libraries in ASIC.〔Mehrotra, Alok; Van Ginneken, Lukas P P P; Trivedi, Yatin. ("Design flow and methodology for 50M gate ASIC" ), IEEE Conference Publications,ISBN 0-7803-7659-5〕 This flexibility is missing for Semi-Custom flows like FPGA (e.g. Altera). 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Physical design (electronics)」の詳細全文を読む スポンサード リンク
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